Package structure with fan-out structure

ABSTRACT

A package structure is provided. The package structure includes a first redistribution structure and a second redistribution structure over the first redistribution structure. The package structure also includes. The package structure further includes a semiconductor chip between the first redistribution structure and the second redistribution structure. In addition, the package structure includes a protective layer surrounding the semiconductor chip and a conductive structure penetrating through the protective layer. The conductive structure has a solder element and a conductive pillar, the conductive pillar has a first end and a second end, and the first end is between the second end and the solder element. The solder element has a protruding portion extending from an interface between the conductive pillar and the solder element towards the second end. A terminal of the protruding portion is vertically between the first end and the second end.

PRIORITY CLAIM AND CROSS-REFERENCE

This Application is a Divisional of U.S. application Ser. No.16/437,297, filed on Jun. 11, 2019, which claims the benefit of U.S.Provisional Application No. 62/752,387, filed on Oct. 30, 2018, theentirety of which are incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment. The fabrication of the semiconductor devicesinvolves sequentially depositing insulating or dielectric layers,conductive layers, and semiconductor layers over a semiconductorsubstrate, and patterning the various material layers using lithographyand etching processes to form circuit components and elements on thesemiconductor substrate.

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallows more components to be integrated into a given area. The number ofinput and output (I/O) connections is significantly increased. Smallerpackage structures, which utilize less area or have lower heights, aredeveloped to package the semiconductor devices.

New packaging technologies have been developed to improve the densityand functionality of semiconductor devices. These relatively new typesof packaging technologies for semiconductor devices face manufacturingchallenges.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1J are cross-sectional views of various stages of a process forforming a package structure, in accordance with some embodiments.

FIGS. 2A-2B are cross-sectional views of various stages of a process forforming a package structure, in accordance with some embodiments.

FIG. 3 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments.

FIG. 4 is a top view of a portion of a package structure, in accordancewith some embodiments.

FIG. 5 is a cross-sectional view of a package structure, in accordancewith some embodiments.

FIG. 6 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments.

FIG. 7 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Embodiments of the disclosure may be applied in 3D packaging or 3D ICdevices. Other features and processes may also be included. For example,testing structures may be included to aid in the verification testing ofthe 3D packaging or 3DIC devices. The testing structures may include,for example, test pads formed in a redistribution layer or on asubstrate that allows the testing of the 3D packaging or 3DIC, the useof probes and/or probe cards, and the like. The verification testing maybe performed on intermediate structures as well as the final structure.Additionally, the structures and methods disclosed herein may be used inconjunction with testing methodologies that incorporate intermediateverification of known good dies to increase the yield and decreasecosts.

The term “substantially” herein, such as in “substantially flat” or in“substantially consists”, etc., will be understood by the person skilledin the art. In some embodiments the adjective substantially may beremoved. Where applicable, the term “substantially” may also includeembodiments with “entirely”, “completely”, “all”, etc. Where applicable,the term “substantially” may also relate to 90% or higher, such as 95%or higher, especially 99% or higher, including 100%. Furthermore, termssuch as “substantially parallel” or “substantially perpendicular” are tobe interpreted as not to exclude insignificant deviation from thespecified arrangement and may include for example deviations of up to10°. The word “substantially” does not exclude “completely” e.g. acomposition which is “substantially free” from Y may be completely freefrom Y.

Terms such as “about” in conjunction with a specific distance or sizeare to be interpreted so as not to exclude insignificant deviation fromthe specified distance or size and may include for example deviations ofup to 10%. The term “about” in relation to a numerical value x may meanx±5 or 10%.

Some embodiments of the disclosure are described. Additional operationscan be provided before, during, and/or after the stages described inthese embodiments. Some of the stages that are described can be replacedor eliminated for different embodiments. Additional features can beadded to the semiconductor device structure. Some of the featuresdescribed below can be replaced or eliminated for different embodiments.Although some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

FIGS. 1A-1J are cross-sectional views of various stages of a process forforming a package structure, in accordance with some embodiments. Asshown in FIG. 1A, an interconnection structure 102 is formed over thecarrier substrate 100, in accordance with some embodiments. Theinterconnection structure 102 may be used as a redistribution structurefor routing. Due to the interconnection structure 102, a packagestructure with a fan-out structure may be formed. The interconnectionstructure 102 includes multiple insulating layers 104 and multipleconductive features 106, as shown in FIG. 1A. The conductive features106 may include conductive lines, conductive vias, and/or conductivepads. The interconnection structure 102 also includes conductivefeatures 107A and 107B that are used to hold or receive other elementssuch as conductive pillars or semiconductor dies.

In some embodiments, some of the conductive features 107A and 107B areexposed at or protrude from the topmost surface of the insulating layers104. The exposed or protruding conductive features 107A and 107B mayserve as bonding pads where conductive bumps (such as tin-containingsolder bumps) and/or conductive pillars (such as copper pillars) will beformed later.

The insulating layers 104 may be made of or include one or more polymermaterials. The polymer material(s) may include polybenzoxazole (PBO),polyimide (PI), one or more other suitable polymer materials, or acombination thereof. In some embodiments, the polymer material isphotosensitive. In some embodiments, some or all of the insulatinglayers 104 are made of or include dielectric materials other thanpolymer materials. The dielectric material may include silicon oxide,silicon carbide, silicon nitride, silicon oxynitride, one or more othersuitable materials, or a combination thereof.

The conductive features 106 may include conductive lines providingelectrical connection in horizontal directions and conductive viasproviding electrical connection in vertical directions. The conductivefeatures 106 may be made of or include copper, aluminum, gold, cobalt,titanium, graphene, one or more other suitable conductive materials, ora combination thereof.

The formation of the interconnection structure 102 may involve multipledeposition or coating processes, multiple patterning processes, and/ormultiple planarization processes.

The deposition or coating processes may be used to form insulatinglayers and/or conductive layers. The deposition or coating processes mayinclude a spin coating process, an electroplating process, anelectroless process, a chemical vapor deposition (CVD) process, aphysical vapor deposition (PVD) process, an atomic layer deposition(ALD) process, one or more other applicable processes, or a combinationthereof.

The patterning processes may be used to pattern the formed insulatinglayers and/or the formed conductive layers. The patterning processes mayinclude a photolithography process, an energy beam drilling process(such as a laser beam drilling process, an ion beam drilling process, oran electron beam drilling process), an etching process, a mechanicaldrilling process, one or more other applicable processes, or acombination thereof.

The planarization processes may be used to provide the formed insulatinglayers and/or the formed conductive layers with planar top surfaces tofacilitate subsequent processes. The planarization processes may includea mechanical grinding process, a chemical mechanical polishing (CMP)process, one or more other applicable processes, or a combinationthereof. In some other embodiments, the planarization process is notperformed.

However, many variations and/or modifications can be made to embodimentsof the disclosure. In some other embodiments, the interconnectionstructure 102 is not formed.

Afterwards, conductive structures 108 are formed over the conductivefeatures 107A, as shown in FIG. 1A in accordance with some embodiments.In some embodiments, the conductive structures 108 are used for signaltransmission. In some embodiments, the conductive structures 108 areconductive pillars. In some embodiments, the conductive structures 108have substantially straight sidewalls. The sidewalls of the conductivestructures 108 may be substantially perpendicular to the top surface ofthe carrier substrate 100. The conductive structures 108 may be made ofor include copper, aluminum, titanium, cobalt, gold, tin-containingalloys, one or more other suitable materials, or a combination thereof.

The conductive structures 108 may be formed using an electroplatingprocess, an electroless plating process, a PVD process, a CVD process,one or more other applicable processes, or a combination thereof. Insome other embodiments, the conductive structures 108 are picked andplaced onto the exposed conductive features 107A. Tin-containing solderelements may be used to affix the conductive structures 108.

As shown in FIG. 1B, a semiconductor device such as a semiconductor die110 is disposed over the carrier substrate 100, in accordance with someembodiments. In some embodiments, the semiconductor die 110 is disposedonto the exposed conductive features 107B. The semiconductor die 110 maybe a system-on-chip (SoC) chip. In some other embodiments, the element110 is a system on integrated circuit (SoIC) device that includes two ormore chips with integrated function. In these cases, the referencenumber “110” is used to designate a semiconductor device. Thesemiconductor device may include one die, multiple dies, orsystem-on-integrated-circuit chip device. For example, the element 110includes a stack of multiple semiconductor dies.

In some embodiments, the semiconductor die 110 is disposed over theinterconnection structure 102 formed over the carrier substrate 100. Insome embodiments, the semiconductor die 110 is bonded to the conductivefeatures 107B of the interconnection structure 102 through bondingstructures 114. The bonding structures 114 may physically andelectrically connect the conductive features 107B and conductivefeatures 112 of the semiconductor die 110. The conductive features 112of the semiconductor die 110 may include conductive pads, conductivepillars, conductive traces, or the like.

In some embodiments, the bonding structures 114 are or include solderbumps such as tin-containing solder bumps. The tin-containing solderbumps may further include copper, silver, gold, aluminum, lead, one ormore other suitable materials, or a combination thereof. In someembodiments, the tin-containing solder bump is lead free. The formationof the bonding structures 114 may involve one or more reflow processesand/or one or more plating processes.

As shown in FIG. 1C, a protective substrate 20 is provided or receivedand is ready to be bonded onto the conductive structures 108, inaccordance with some embodiments. In some embodiments, the protectivesubstrate 20 includes a board 200 and conductive elements 202. The board200 and the conductive elements 202 together form a redistributionstructure that may be used for routing. The board 200 may be made of orinclude a polymer material, a ceramic material, a metal material, asemiconductor material, one or more other suitable materials, or acombination thereof.

For example, the board 200 includes resin, prepreg, glass, and/orceramic. In the cases where the board 200 is made of a metal material ora semiconductor material, dielectric layers may be formed between theboard 200 and the conductive elements 202 to prevent short circuiting.

In some embodiments, the protective substrate 20 includes conductivebumps 204. In some embodiments, the conductive bumps 204 are solderelements made of, for example, a tin-containing solder material. Thetin-containing solder material may further include copper, silver, gold,aluminum, lead, one or more other suitable materials, or a combinationthereof. In some embodiments, the tin-containing solder material is leadfree.

The formation of the conductive bumps 204 may involve one or moreplating processes (such as electroplating processes) and/or one or morereflow processes. The protective substrate 20 also includes conductivefeatures 201 that are used to hold or receive other elements such as theconductive bumps 204.

As shown in FIG. 1C, the protective substrate 20 is positioned to allowthe conductive bumps 204 to be substantially aligned with the conductivestructures 108, in accordance with some embodiments. As mentioned above,in some embodiments, the conductive bumps 204 are tin-containing solderelements which may facilitate a subsequent bonding process.

As shown in FIG. 1D, the protective substrate 20 is disposed over thecarrier substrate 100 to allow conductive structures (such as theconductive bumps 204) of the protective substrate 20 to be in directcontact with the conductive structures 108, in accordance with someembodiments. As shown in FIG. 1D, the bottom surface of the board 200 isseparated from the top surface of the interconnection structure 102 by adistance H₁. In some cases, the distance H₁ may be varied at differentpositions since some of the conductive structures 108 and/or theconductive bumps 204 have different heights.

As shown in FIG. 1E, a thermal reflow process is used to affix theprotective substrate 20 and the conductive structures 108, in accordancewith some embodiments. As mentioned above, in some embodiments theconductive bumps 204 are tin-containing solder bumps. In these cases,solder joints may be formed between the conductive bumps 204 and theconductive structures 108 so as to affix the protective substrate 20 andthe conductive structures 108. As shown in FIG. 1E, after the thermalreflow process, the bottom surface of the board 200 is separated fromthe top surface of the interconnection structure 102 by a distance H₂.In some embodiments, the distance H₂ is slightly shorter than thedistance H₁.

As shown in FIG. 1F, the protective substrate 20 and the carriersubstrate 100 are pressed against each other at an elevated temperature,in accordance with some embodiments. As a result, the protectivesubstrate 20 is bonded to the conductive structures 108. In someembodiments, a thermal compression process is used to achieve thebonding process mentioned above. As shown in FIG. 1F, after the thermalcompression process, the distance between the bottom surface of theboard 200 and the top surface of the interconnection structure 102 isreduced from the distance H₂ to the distance H₃. A space S is definedbetween the protective substrate 20 and the carrier substrate 100, asshown in FIG. 1F. Due to the thermal compression process, bondingstructures constructed by the conductive bumps 204 and the conductivestructures 108 may have a substantially uniform joint height.

In some embodiments, molding elements 180A and 180B are used to applycompression force F to the protective substrate 20 and the carriersubstrate 100 at an elevated temperature. In some embodiments, theelevated temperature is higher than about 120 degrees C. and lower thanthe melting point of the conductive bump 204. In some embodiments, theelevated temperature is in a range from about 120 degrees C. to about200 degrees C. In some other embodiments, the elevated temperature is ina range from about 150 degrees C. to about 180 degrees C.

At elevated temperatures, the conductive bumps 204 may become softerthan their original state at room temperature. Therefore, the softerconductive bumps 204 may be pressed towards the conductive structures108 more easily by the molding elements 180A and 180B. Even if some ofthe conductive structures 108 and/or the conductive bumps 204 havedifferent heights, the thermal compression process may allow thethermally pressed conductive structures 108 and the conductive bumps 204to have substantially the same height. The height H₃ is thereforesubstantially uniform at different positions of the package structure,which facilitates subsequent processes.

In some cases, if the elevated temperature is lower than about 120degrees C., the conductive bumps 204 may not be soft enough. As aresult, the molding elements 180A and 180B may not be able to press theconductive bumps 204 towards the conductive structures 108. The heightH₃ may not be uniform at different positions.

In some other cases, if the elevated temperature is higher than about200 degrees C., the conductive bumps 204 may become too soft. Theconductive bumps 204 may not be able to sustain the applied compressionforce F and might collapse. The height H₃ may still not be uniform atdifferent positions.

FIG. 3 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments. In some embodiments, FIG. 3 is anenlarged view showing a portion of the package structure shown in FIG.1F.

In some embodiments, due to the characteristics of the thermalcompression process, the conductive bumps 204 are pressed to formprotruding portions 206, as shown in FIG. 3. Each of the protrudingportions 206 extends downwards from the interface 208 between thecorresponding conductive bump 204 and the corresponding conductivestructure 108, as shown in FIG. 3 in accordance with some embodiments.

In some embodiments, the protruding portion 206 partially overlaps orpartially covers the sidewall S₂ of the conductive structure 108 with anobservation direction perpendicular to the sidewall S₂ of the conductivestructure 108, as shown in FIG. 3. As shown in FIG. 3, the protrudingportion 206 has an inner sidewall S₁. In some embodiments, the innersidewall S₁ of the protruding portion 206 is separated from the sidewallS₂ of the conductive structure 108.

A recess 210 is defined by the inner sidewall S₁ of the protrudingportion 206 and the sidewall S₂ of the conductive structure 108, asshown in FIG. 3. In some embodiments, the protruding portion 206 of theconductive bump 204 continuously surrounds the recess 210. In someembodiments, the recess 210 continuously surrounds a portion of theconductive structure 108.

FIG. 4 is a top view of a portion of a package structure, in accordancewith some embodiments. In some embodiments, FIG. 4 shows a top view ofthe conductive structure 108 and the conductive bump 204 with anobservation direction from the bottom of the conductive structure 108towards the conductive bump 204. For simplicity and clarity, only theconductive structure 108 and the conductive bump 204 are illustrated inFIG. 4.

In FIG. 4, the circle P shows the top view of the bottommost portion ofthe protruding portion 206. As shown in FIG. 4, the bottom of theprotruding portion 206 of the conductive bump 204 continuously surroundsthe recess 210 and the conductive structure 108. In some embodiments,the recess 210 continuously surrounds a portion of the conductivestructure 108.

In some embodiments, the inner sidewall S₁ of the protruding portion 206and the sidewall S₂ of the conductive structure 108 together define anangle θ₁, as shown in FIG. 3. In some embodiments, the angle θ₁ is anacute angle. In some embodiments, the angle θ₁ is in a range from about5 degrees to about 25 degrees. In some other embodiments, the angle θ₁is in a range from about 10 degrees to about 20 degrees.

As shown in FIG. 3, the conductive bump 204 also includes side surfacesS₃ and S₄ at a corner portion of the conductive bump 204 near theconductive feature 201. The side surfaces S₃ and S₄ together define anangle θ₂, as shown in FIG. 3. In some embodiments, the angle θ₂ issubstantially equal to 90 degrees. In some other embodiments, the angleθ₂ is greater than 90 degrees. The angle θ₂ may be in a range from about90 degrees to about 140 degrees.

FIG. 7 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments. In some embodiments, FIG. 7 is anenlarged view showing a portion of the package structure shown in FIG.1F. In some embodiments, an opening of the board 200 that exposes theconductive feature 201 has slanted sidewalls. In these cases, the angleθ₂ is greater than 90 degrees.

As shown in FIG. 3 or FIG. 7, similar to the angles θ₁ and θ₂, anglesθ₁′ and θ₂′ are also defined on the opposite side of the conductive bump204. In some embodiments, the angle θ₁′ is substantially equal to theangle θ₁. In some other embodiments, the angles θ₁ and θ₁′ are differentfrom each other. In some embodiments, the angle θ₂′ is substantiallyequal to the angle θ₂. In some other embodiments, the angles θ₂ and θ₂′are different from each other.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, one or both of the angles θ₁ andθ₁′ has/have a different angle range. For example, one or both of theangles θ₁ and θ₁′ may be greater than about 90 degrees. One or both ofthe angles θ₁ and θ₁′ may be in a range from about 90 degrees to about140 degrees.

Referring to FIG. 1G, a protective layer 116 is formed to surround thesemiconductor die 110 and the conductive structures 108, in accordancewith some embodiments. In some embodiments, the protective layer 116 isin direct contact with the conductive structures 108 and the conductivebumps 204. In some embodiments, the protective layer 116 is in directcontact with the semiconductor die 110. In some embodiments, a portionof the protective layer 116 fills the recess 210 defined by theprotruding portions 206 and the conductive structures 108 In someembodiments, the protective layer 116 is in direct contact with theinner sidewalls S₁ of the protruding portions 206.

In some embodiments, the protective layer 116 is made of or includes aninsulating material such as a molding material. The molding material mayinclude a polymer material, such as an epoxy-based resin with fillersdispersed therein. In some embodiments, a molding material (such as aliquid molding material) is introduced or injected into the space Sbetween the protective substrate 20 and the carrier substrate 100. Insome embodiments, the molding material is introduced to surround thesemiconductor die 110 while the protective substrate 20 and the carriersubstrate 100 are pressed against each other at an elevated temperature.

In some embodiments, a thermal process is then used to cure the liquidmolding material and to transform it into the protective layer 116. Insome other embodiments, the liquid molding material is cured between themolding elements 180A and 180B at an elevated temperature.Alternatively, the temperature may be increased to cure the liquidmolding material. Because the protective layer 116 is formed during thethermal compression process, the compression force F from the moldingelements 180A and 180B may be used to reduce warpage caused due tothermal expansion differences between different materials. Interfaceadhesion between different materials may be greatly enhanced since allelements are kept stable by the molding elements 180A and 180B. Thequality and reliability of the formed package structure aresignificantly improved.

In some embodiments, after the formation of the protective layer 116,the formed package structure is removed from the molding elements 180Aand 180B. Afterwards, the formed package structure is turned upside downand disposed onto a tape carrier 118, as shown in FIG. 1H in accordancewith some embodiments.

As shown in FIG. 1I, the carrier substrate 100 is removed, in accordancewith some embodiments. Afterwards, conductive bumps 120 are formed, asshown in FIG. 1J in accordance with some embodiments. In someembodiments, the conductive bumps 120 are or include solder bumps suchas tin-containing solder bumps. The tin-containing solder bumps mayfurther include copper, silver, gold, aluminum, lead, one or more othersuitable materials, or a combination thereof. In some embodiments, thetin-containing solder bump is lead free.

In some embodiments, solder balls (or solder elements) are disposed ontothe exposed conductive features 106 after the removal of the carriersubstrate 100. A reflow process is then carrier out to melt the solderballs into the conductive bumps 120. In some other embodiments, underbump metallization (UBM) elements are formed over the exposed conductivefeatures 106 before the solder balls are disposed. In some otherembodiments, solder elements are electroplated onto the exposedconductive features 106. Afterwards, a reflow process is used to meltthe solder element to form the conductive bumps 120. In someembodiments, a singulation process is then carrier out to saw throughthe formed structure. As a result, multiple separate package structuresare formed. Afterwards, the tape carrier 118 is removed. In FIG. 1J, oneof the package structures is shown.

Many variations and/or modifications can be made to embodiments of thedisclosure. FIGS. 2A-2B are cross-sectional views of various stages of aprocess for forming a package structure, in accordance with someembodiments. As shown in FIG. 2A, a structure similar to the structureshown in FIG. 1B is provided or formed, in accordance with someembodiments.

As shown in FIG. 2A, an underfill layer 302 is formed to protect thebonding structures 114, in accordance with some embodiments. Theunderfill layer 302 is made of or includes one or more polymermaterials. The underfill layer 302 may include an epoxy-based resin. Insome embodiments, the underfill layer 302 further includes fillersdispersed in the epoxy-based resin. In some embodiments, the formationof the underfill layer 302 involves an injecting process, a dispensingprocess, a film lamination process, an application process, one or moreother applicable processes, or a combination thereof. In someembodiments, a thermal curing process is then used to complete theformation of the underfill layer 302.

Afterwards, processes similar to those illustrated in FIGS. 1C-1J areperformed to form a package structure, as shown in FIG. 2B in accordancewith some embodiments. In some embodiments, the bonding structures 114are not in direct contact with the protective layer 116. The bondingstructures 114 are separated from the protective layer 116 by theunderfill layer 302.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, the conductive structure 108 isnot formed. FIG. 5 is a cross-sectional view of a package structure, inaccordance with some embodiments. As shown in FIG. 5, the conductivebumps 204 are bonded to the exposed conductive features 106 of theinterconnection structure 102.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, similar to the embodimentsillustrated in FIG. 2B, an underfill layer is formed to protect thebonding structures 114 before the formation of the protective layer 116.In these cases, the bonding structures 114 are not in direct contactwith the protective layer 116. The bonding structures 114 are separatedfrom the protective layer 116 by the underfill layer 302.

FIG. 6 is a cross-sectional view of a portion of a package structure, inaccordance with some embodiments. In some embodiments, FIG. 6 is anenlarged view showing a portion of the package structure shown in FIG.5.

As shown in FIG. 6, a surface of the conductive bump 204 near theconductive feature 107A and a surface of the conductive feature 107Atogether define an angle θ₃. In some embodiments, the angle θ₃ is anacute angle. In some embodiments, the angle θ₃ is in a range from about30 degrees to about 60 degrees. In some other embodiments, the angle θ₃is in a range from about 40 degrees to about 50 degrees.

As shown in FIG. 6, the conductive bump 204 includes side surfaces S₃and S₄ at a corner portion of the conductive bump 204 near theconductive feature 201. The side surfaces S₃ and S₄ together define anangle θ₂, as shown in FIG. 6. In some embodiments, the angle θ₂ issubstantially equal to 90 degrees. In some other embodiments, the angleθ₂ is greater than 90 degrees. The angle θ₂ may be in a range from about90 degrees to about 140 degrees.

As shown in FIG. 6, similar to the angles θ₃ and θ₂, angles θ₃′ and θ₂′are also defined on the opposite side of the conductive bump 204. Insome embodiments, the angle θ₃′ is substantially equal to the angle θ₃.In some other embodiments, the angles θ₃ and θ₃′ are different from eachother. In some embodiments, the angle θ₂′ is substantially equal to theangle θ₂. In some other embodiments, the angles θ₂ and θ₂′ are differentfrom each other.

Embodiments of the disclosure form a package structure using a thermalcompression process. A semiconductor die is disposed over a carriersubstrate with conductive pillars formed thereon. A protective substrateis bonded onto the conductive pillars through solder bumps using thethermal compression process. Due to the characteristics of the thermalcompression process, the solder bumps are pressed towards the conductivepillars to ensure that each of the bonding structures including thesolder bumps and the conductive pillars are controlled to havesubstantially the same height. A protective layer is then formed tosurround the semiconductor die while the thermal compression process isstill applied to the carrier substrate and the protective substrate.Because the protective layer is formed during the thermal compressionprocess, the warpage of the package structure would be significantlyreduced. Interface adhesion between different materials may be greatlyenhanced since all elements are kept stable. The quality and reliabilityof the formed package structure are significantly improved.

In accordance with some embodiments, a method for forming a packagestructure is provided. The method includes forming a conductivestructure over a carrier substrate and disposing a semiconductor dieover the carrier substrate. The method also includes pressing aprotective substrate against the carrier substrate at an elevatedtemperature to bond the protective substrate to the conductivestructure. The method further includes forming a protective layer tosurround the semiconductor die.

In accordance with some embodiments, a method for forming a packagestructure is provided. The method includes forming a first conductivestructure over a carrier substrate and disposing a semiconductor dieover the carrier substrate. The method also includes disposing aprotective substrate over the carrier substrate and the semiconductordie. As a result, a second conductive structure of the protectivesubstrate is in direct contact with the first conductive structure. Themethod further includes pressing the protective substrate and thecarrier substrate against each other at an elevated temperature toreduce a distance between the carrier substrate and the protectivesubstrate. In addition, the method includes forming a protective layerto surround the semiconductor die.

In accordance with some embodiments, a package structure is provided.The package structure includes a first redistribution structure and asecond redistribution structure over the first redistribution structure.The package structure also includes a semiconductor die between thefirst redistribution structure and the second redistribution structure.The package structure further includes a protective layer surroundingthe semiconductor die. In addition, the package structure includes aconductive structure penetrating through the protective layer. Theconductive structure has a solder element and a conductive pillar. Thesolder element has a protruding portion extending downwards from aninterface between the conductive pillar and the solder element.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A package structure, comprising: a firstredistribution structure; a second redistribution structure over thefirst redistribution structure; a semiconductor chip between the firstredistribution structure and the second redistribution structure; aprotective layer surrounding the semiconductor chip; and a conductivestructure penetrating through the protective layer, wherein theconductive structure comprises a solder element and a conductive pillar,the conductive pillar has a first end and a second end, the first end isbetween the second end and the solder element, the solder element has aprotruding portion extending from an interface between the conductivepillar and the solder element towards the second end, and a terminal ofthe protruding portion is vertically between the first end and thesecond end.
 2. The package structure as claimed in claim 1, wherein theprotruding portion of the solder element has an inner sidewall, and theinner sidewall and a sidewall of the conductive pillar define an acuteangle.
 3. The package structure as claimed in claim 1, wherein theprotruding portion of the solder element laterally and partiallysurrounds of a sidewall of the conductive pillar.
 4. The packagestructure as claimed in claim 1, wherein the solder element has a firstside surface extending into the second redistribution structure, thesolder element has a second side surface extending along a bottomsurface of the second redistribution structure, the first side surfaceand the second side surface define an angle, and the angle is in a rangefrom about 90 degrees to about 140 degrees.
 5. The package structure asclaimed in claim 1, further comprising: connectors between thesemiconductor chip and the first redistribution structure; and anunderfill layer between the connectors and the protective layer.
 6. Thepackage structure as claimed in claim 5, wherein the conductive pillaris between the first redistribution structure and the solder element. 7.The package structure as claimed in claim 5, wherein the interfacebetween the conductive pillar and the solder element is verticallybetween a top surface of the semiconductor chip and a bottom surface ofthe semiconductor chip.
 8. The package structure as claimed in claim 1,wherein a portion of the protective layer is between the protrudingportion of the solder element and the conductive pillar.
 9. The packagestructure as claimed in claim 1, wherein the protective layer laterallysurrounds the protruding portion of the solder element.
 10. The packagestructure as claimed in claim 1, wherein the protruding portion of thesolder element continuously surrounds the conductive pillar.
 11. Apackage structure, comprising: a first redistribution structure; asecond redistribution structure over the first redistribution structure;a semiconductor chip between the first redistribution structure and thesecond redistribution structure; a conductive pillar bonded with thefirst redistribution structure; a solder element bonded with the secondredistribution structure, wherein the solder element has a protrudingportion extending towards the first redistribution structure andextending across an end of the conductive pillar; and a protective layersurrounding the semiconductor chip, the solder element, and theconductive pillar, wherein the protective layer fills a recess betweenthe protruding portion of the solder element and the conductive pillar.12. The package structure as claimed in claim 11, wherein a portion ofthe protective layer is between the protruding portion of the solderelement and the first redistribution structure.
 13. The packagestructure as claimed in claim 11, wherein the conductive pillar iscloser to the first redistribution structure than the solder element.14. The package structure as claimed in claim 11, wherein the protrudingportion of the solder element has an inner sidewall, and the innersidewall and a sidewall of the conductive pillar define an acute angle.15. The package structure as claimed in claim 11, wherein the protectivelayer is in direct contact with the solder element and the conductivepillar.
 16. A package structure, comprising: a first redistributionstructure; a second redistribution structure over the firstredistribution structure; a semiconductor chip between the firstredistribution structure and the second redistribution structure; aconductive pillar bonded with the first redistribution structure; and asolder element bonded with the second redistribution structure, whereinthe solder element has a protruding portion extending towards the firstredistribution structure to exceed an end of the conductive pillar and,and the conductive pillar is closer to the first redistributionstructure than the solder element.
 17. The package structure as claimedin claim 16, further comprising a protective layer surrounding thesemiconductor chip, wherein a portion of the protective layer is betweenthe conductive pillar and the protruding portion of the solder element.18. The package structure as claimed in claim 17, wherein the protectivelayer is in direct contact with the protruding portion of the solderelement.
 19. The package structure as claimed in claim 16, wherein thesemiconductor chip is bonded with the first redistribution structure.20. The package structure as claimed in claim 16, wherein the protrudingportion of the solder element has an inner sidewall, and the innersidewall and a sidewall of the conductive pillar define an acute angle.